Ultra-large scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors on a substrate. The transistors are generally metal oxide semiconductor field effect transistors (MOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material.
Generally, the gate conductor is a polysilicon or polysilicon/germanium (Si.sub.x Ge.sub.(1-x)) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
The polysilicon and polysilicon/germanium gate materials are heavily doped (e.g., P+ or N+) to increase their conductivity. According to conventional processes, the dopant implant projection is positioned at a half-depth of the gate material (i.e., gate electrode) thickness to reduce the possibility of dopant diffusion through the thin gate oxide into the channel. Dopant diffusion through the thin gate oxide can adversely affect the predictability of the design and the operability of the circuit. In conventional processes, dopant distribution and gate material have a Gaussian-like profile (the dopant concentration is greatest in the center of the gate material). Accordingly, the dopant concentration near the gate electrode/gate oxide interface is relatively low. The relatively low dopant concentration near the gate electrode and gate oxide interface results in "gate-depletion effect" which is a major problem in complementary MOS (CMOS) processes which manufacture small-scale transistors.
Conventional processes for fabricating transistors have a limited thermal budget so that shallow junctions can be effectively formed. Shallow junctions are necessary for transistors with very small size in ULSI circuits. Dopant implanted into the gate material is often not sufficiently activated due to the limited thermal budget available. The low electrically activated dopant concentration near the gate material/gate oxide interface, combined with the gate depletion effect, causes higher resistance in the polysilicon or polysilicon/germanium gate material. The higher resistance results in a greater voltage drop between the center of the gate conductor and the gate oxide. The greater voltage drop causes a loss of effective voltage bias, which in turn degrades MOSFET drive current and speed and increases the amount of power consumed by the transistor.
Thus, there is a need for a process which can manufacture a gate conductor having a box-like dopant profile. Further still, there is a need for a gate conductor that has a relatively low thermal budget. Even further still, there is a need for a polysilicon/germanium gate conductor that can be efficiently manufactured.